The present invention relates to transmission of data on a subscriber loop in a public network such as, for example, a telephone network. More specifically, the present invention provides an improvement of standard single pair digital subscriber line (SDSL) technology.
A wide variety of technologies and transmission standards have been developed for transmission of data via currently existing public network resources. A substantial portion of these resources comprise copper twisted pair transmission lines. This is especially true for the final connections to individual subscribers, i.e., subscriber loops. Without other limitations such as core network filters, such copper lines can achieve practical data rates on the order of tens of megabits per second (Mbps). Of course, substantial attenuation occurs at the higher data rates thereby limiting the length of the subscriber loop which may be serviced at such rates. For example, 24 gauge copper supports reliable transmission of data at the DS1 standard, i.e., 1.544 kbps, also commonly referred to as T1, for up to 12,000 feet. By contrast, the same 24 gauge copper will only support the STS-1 standard, i.e., 51.840 Mbps, for lines of less than 1000 feet.
The term xe2x80x9cdigital subscriber linexe2x80x9d (DSL) refers to a modem or modem pair connected by one or more twisted pairs having a specific data frame format and associated transmission rate. The first digital subscriber line technology, referred to as IDSL, corresponds to what is also known as basic rate ISDN. IDSL technology transmits duplex data at 144 kbps over copper lines using a 2B1Q modulation scheme. The modems multiplex and demultiplex the data stream into two B channels (64 kbps each) and a D channel (16 kbps) as described in ANSI T1.601, the entirety of which is incorporated herein by reference for all purposes.
High data rate digital subscriber lines (HDSL) are related to the earlier IDSL using the same modulation scheme to transmit data at the T1 data rate over two twisted pairs as described in ANSI Committee T1 TR-28, the entirety of which is incorporated herein by reference for all purposes. A single pair digital subscriber line (SDSL) is a single pair version of HDSL, i.e., transmitting data at one-half the T1 data rate, i.e., 768 kbps, over a single twisted pair. For both HDSL and SDSL and as shown in FIG. 1, data are organized into 6 ms frames 102 comprising alternating overhead and payload sections 104 and 106. The four payload sections 106 each include twelve 97-bit payload blocks 108, 96 bits (110) of which are data and one bit (112) of which represents block overhead. This works out to the well known data rate of 768 kbps. Overhead sections 104 and 112 represent an additional 16 kbps for an actual transmission rate of 784 kbps.
FIG. 2 is a simplified block diagram of one portion 200 of a standard SDSL, configured as a HDSL Terminal Unitxe2x80x94Central Office (HTU-C) or public branch exchange (represented by modem 204). The central office typically transmits data via twisted pair line 216 to a subscriber premises (represented by modem 206, FIG. 3). The data to be transmitted enters framing circuitry 208 of modem 204 at the raw data rate of, for example, 768 kbps. Framing circuitry 208 organizes the incoming data stream into the 6 ms frames described above with reference to FIG. 1. In order to perform this task, the framing circuitry 208 utilizes a signal generated from a 768 kHz oscillator 210. The signal provided by oscillator 210 to framing circuitry 208 functions as a data clock, and is used in communicating and synchronizing with incoming raw data on line 201. While the framing circuitry 208 organizes the incoming data stream into the 6 ms frames, it generates frame overhead data, which is multiplexed with the raw data, and inserted into the frame at a rate of 16 kbps. During the time that the frame overhead data is being inserted into the frame, the incoming raw data is queued in a FIFO buffer. When the insertion of frame overhead data is finished, the data from the FIFO buffer is then inserted into the frame, followed by incoming raw data from line 201. The framed data are then sent to bit pump 212 where, using a 784 kHz oscillator 214, they are encoded according to the 2B1Q modulation scheme and transmitted via twisted pair line 216 to the subscriber premises.
As shown in FIG. 2, a conventional HTU-C system, requires two different clock sources: one for the data rate and one for the signaling rate. The solution to this requirement is classically solved via two externally provided clock signals, each signal being generated from a separate oscillator. In FIG. 2, the 768 kHz oscillator 210 is utilized as a data clock by the framing circuitry for generating the data frames and for communicating and synchronizing with the incoming raw data. The 784 kHz oscillator 214 is utilized as a signaling clock by the bit pump for modulating the data frames according to the 2B1Q modulation scheme. However, use of two separate clock sources increases cost, complexity, power consumption, and space utilization of the DSL modem. What is desirable, therefore, is to provide a DSL modem having reduced, cost, complexity, power consumption, and space requirements compared to conventional DSL modems configured as HTU-C devices.
This and art additional objects are accomplished by the various aspects of the present invention wherein, briefly, according to a principal aspect, a digital subscriber line (DSL) modem is provided wherein the clocking signals utilized by the framing circuitry and bit pump are both derived from a single external clock source.
Accordingly, a first aspect of the present invention is directed to a DSL modem for receiving an incoming data stream and generating a sequence of data frames for a digital subscriber line. The modem comprises a clock source for providing a first clock signal; a modulation circuit; and framing circuit which provides a receiver overhead signal for indicating the incorporation of frame overhead bits into generated data frames; and a clocking circuit adapted to receive the first clock signal and the receiver overhead signal for providing a second clock signal to the framing circuit. The clocking circuit includes logic means for combining the first clock signal and the receiver overhead signal to generate the second clock signal, wherein the generated second clock signal has a specific timing relationship to the first clock signal and the receiver overhead signal such that, while the receiver overhead signal is inactive, a second clock signal is active at a frequency substantially equal to the frequency of the first clock signal, and while the receiver overhead signal is active, a second clock signal is inactive. This generated second clock signal is utilized by the framing circuit for communication with the incoming data stream.
A second aspect of the present invention is directed to an apparatus included within a DSL modem. The DSL modem includes a modulation circuit; a clock source for providing a first clock signal; and a framing circuit which provides a receiver overhead signal for indicating the incorporation of frame overhead bits into each data frame. The framing circuit further includes a pulse code multiplexed (PCM) interface circuit for communication with incoming PCM data. The apparatus comprises a clocking circuit adapted to receive the first clock signal and the receiver overhead signal for providing a second clock signal to the framing circuit The clocking circuit includes logic means for logically combining the first clock signal and the receiver overhead signal to generate the second clock signal, wherein the timing of the generated second clock signal is such that, while the receiver overhead signal is inactive, the second clock signal is active at a frequency substantially equal to the frequency of he first clock signal, and while the receiver overhead signal is active, the second clock frequency is inactive. This generated second clock signal is utilized by the framing circuit for communication with the PCM data.
A third aspect of the present invention is directed to a digital subscriber line apparatus for receiving an incoming data stream and generating a sequence of data frames for output to a digital subscriber line. The DSL apparatus comprises a clock source for providing one of a plurality of clock signals, wherein the one clock signal has an associated frequency of n Hz; a modulation circuit; a framing circuit which provides a receiver overhead signal for indicating the incorporation of frame overhead bits into each sequence of data frames, wherein the receiver overhead signal has an associated average frequency of m Hz; and a clocking circuit adapted to receive the one clock signal and the receiver overhead signal for providing a second clock signal to the framing circuit. The clocking circuit includes logic means for combining the one clock signal and the receiver overhead signal to generate a second clock signal such that while the receiver overhead signal is inactive, the second clock signal is active at a frequency substantially equal to n Hz, and while the receiver overhead signal is active, the second clock signal is inactive. The resulting second clock signal generated by the clocking circuit has an associated average frequency of (n-m) Hz. This second clock signal is utilized by the framing circuit in generating the sequence of data frames, wherein each of the sequence of generated data frames has an associated average frequency of (n-m) Hz.
A fourth aspect of the present invention is directed to a method for generating a second clock signal to be used by a framing circuit in a DSL modem configured as an HTU-C device. The method includes receiving a first clock signal from a first clock source; receiving a receiver overhead signal provided by the framing circuitry; combining the first clock signal with the receiver overhead signal to generate a second clock signal such that, while the receiver overhead signal is inactive, the second clock signal is active at a frequency substantially equal to the frequency of the first clock signal, and while the receiver overhead signal is active, the second clock signal is inactive; and providing the second clock signal to the framing circuit.
A fifth aspect of the present invention is directed to a method for providing a framing circuit with a data clock signal for use in generating a plurality of data frames, wherein the data clock signal is derived from a single clock source. The method includes receiving a first clock signal from a first clock source; receiving a receiver overhead signal from a framing circuit; providing an active data clock signal to the framing circuit while the receiver overhead signal is inactive, wherein the data clock signal has an associated frequency substantially equal to the frequency of the first clock signal; and providing an inactive data clock signal to the framing circuit while the receiver overhead signal is active.
A sixth aspect of the present invention is directed to a method for generating a plurality of data frames in a DSL modem configured as an HTU-C device using a single clock source. The method includes the steps of receiving a first clock signal from a single clock source; receiving a receiver overhead signal from framing circuitry within the DSL modem; and using the first clock signal and receiver overhead signal to clock data into one of the plurality of data frames at a data rate substantially equal to the frequency of the first clock signal only during time intervals when frame overhead bits are not being inserted into the one data frame.
In accordance with the aspects described above, the present invention provides numerous benefits when compared to conventional HTU-C devices which utilize two externally inserted clock signals for generating the data rate and signaling rate, respectively. First, the technique of the present invention for clocking both the data rate and signaling rate from a single external clocking source precludes the need for a separate oscillator or for a separate data clock source. The use of a single clock source or oscillator in the DSL modem of the present invention results in a reduction of space, cost, complexity, and power consumption over conventional DSL modems configured as HTU-C devices. Additionally, as described in greater detail below, the generated data clock signal of the present invention is only active during times when overhead bits are not being inserted in to the data frame by the framing circuitry. This means that incoming data bits are generally clocked into the framing circuit when the framing circuit is ready to receive the data bits, and not at times when the framing circuit is inserting frame overhead bits into the data frame. Consequently, the FIFO buffer within the framing circuitry may be reduced in size since fewer, if any, data bits are clocked into the framing circuitry while the framing circuitry is inserting frame overhead bits into the data frame.
Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.